1. Technical Field
The present invention relates to memory cell power supply in a semiconductor memory, and more particularly, to a memory cell power switching circuit in a volatile semiconductor memory device, such as a static random access memory (SRAM), and a method for applying a memory cell power voltage.
2. Discussion of Related Art
As processor based systems such as personal computers and electronic communication devices achieve higher performance, greater speed and higher-integration, the performance of volatile semiconductor memory devices such as static random access memories (SRAMs) has correspondingly been increased. In a semiconductor memory device used in mobile electronic devices such as a handheld phone or a notebook computer, low power consumption is especially desirable. Accordingly semiconductor manufactures continuously endeavor to reduce the operation current and standby current of memory devices, to provide a mobile-oriented low-power solution.
To reduce standby current in an SRAM, a technique is known in the art of applying a voltage smaller than a normal operation voltage in a standby state, (i.e., not a operating state in which data input and output is performed). In such a technique, the current characteristic of a memory device may be deteriorated due to very great load capacitance when the standby state is switched to the operating state. Thus, when there is a transition between the operation modes, a long time (and current) is needed to transit from the standby voltage (a relatively smaller than the operation voltage) to reach the operation voltage. Thus, while the above-described prior art can reduce the standby current there may be degradation of a device current characteristic, and the prior art is not optimal for employment in several fields.
FIG. 1 is a schematic circuit diagram showing a (memory) cell core circuit of a conventional SRAM (static random access memory). In FIG. 1, is one representative bit line pair (BL, BLB) is shown. It is to be noted that a plurality of memory cells associated with the same bit line pair (BL, BLB) together with a plurality of memory cells associated with other bit line pairs may form a memory cell block; and a plurality of memory cell blocks may form one memory cell array.
Referring to FIG. 1, a plurality (n) of memory cells 2 (including MC #n) are connected between the pair of bit lines BL and BLB. The circuit of each of the unit memory cells 2 may be implemented as a full CMOS SRAM cell including six transistors (T1 to T6) as well known in the art. Each SRAM cell includes access transistors T1 and T2 and load transistors T3 and T4. If the cell pitch (e.g., width) of an SRAM cell is reduced to near the resolution limitation of a photolithography process, the six transistors may be laid out on a different layer, (e.g., not the same layer), in a three-dimensional form.
In FIG. 1, precharge transistors P1 and P2 (for precharging the bit lines BL and BLB, respectively) in response to a control signal PEQ and an equalizing transistor P3 (for maintaining the same voltage level on both of the bit lines BL and BLB). Further, each of word lines W/L1 and W/Ln is connected to the gate of each of the access transistors T1 and T2 in the corresponding unit memory cell 2. Column select gates PG1 and PG2 for electrically connecting or disconnecting between the bit line pair and the data line pair (DL & DLb) are connected to the bit line BL and the complementary bit line BLB, respectively. Both of the column select gates PG1 and PG2 are turned OFF in response to column select signals Yi and Yib in a standby mode and conversely may be turned ON or OFF (in response to column select signals Yi and Yib) during an access operation mode in which reading or writing data is performed.
In FIG. 1, an operating voltage VDD is applied (as a memory cell power voltage) to source terminals of P-type MOS load transistors T3 and T4 (among the transistors T1 through T6 constituting the unit memory cell 2) so that a data storage operation is performed. The operation voltage VDD, applied to the load transistors T3 and T4, should be provided at a predetermined level in an access mode of operation of the memory cell but in the standby mode may be provided at a voltage level lower than the operation voltage (to reduce leakage current flowing through the load transistors T3 and T4). However, if the memory cell power voltage applied to the load transistors T3 and T4 is changed from a (lower) standby voltage to a (higher) operating voltage immediately after the standby mode is changed to the operation mode, load capacitance becomes very large due to a change in a cell power load. This increases the cell wake-up time and degrades an operating characteristic of the semiconductor memory device.
Further, if the device enters a standby mode (when a standby voltage lower than the operation voltage is applied) e.g., whenever a memory cell block including memory cells is not selected during a relatively short period of time, stability of the operation is not guaranteed due to too frequent wake-ups.
Accordingly, there is a need for a technique for reducing standby current without degrading the operating characteristic of a device and for shortening a wake-up time so that a cell power voltage is rapidly recovered to a stable level of an operation voltage without degrading the operating characteristic when a standby mode is switched to an operation mode.